Memory arrays, such as, for example, random access memory (RAM), generally include multiple memory cells, with each memory cell storing a voltage indicative of a logic state (e.g., “0” or “1”) of the cell. Sense amplifiers are used in memory arrays for sensing the output voltage of selected memory cells to thereby read the respective logic states of the cells.
With advancements in technology, memory cells are continually shrinking in size. Unfortunately, the reduction in the size of the memory cell is accompanied by reduction in the sensed voltage from the memory cell. Moreover, as technologies continue to shrink, localized mismatches between transistor devices in the sense amplifier are becoming more significant, thus resulting in increased offset voltage in the sense amplifier. The offset voltage due to local threshold voltage and current mismatches between devices in the sense amplifier, in combination with reduced voltage differential between stored logic states in the memory cell, reduces the resolution during a read operation and underscores the importance of reducing DC offset in the sense amplifier.
U.S. Pat. No. 5,455,798 to McClure discloses arranging a memory array into blocks having redundant columns, each of which can replace a column in any one of the blocks. A plurality of redundant sense amplifiers are included, each associated with selected redundant columns. The redundant sense amplifiers are controlled by redundant column decoders. The coupling of each redundant sense amplifier is controlled by a redundant multiplexer associated with each of the input/output terminals. However, while this approach allows a sense amplifier to be replaced if a defect is found, the level of redundancy required significantly increases the size of the memory array and is therefore undesirable.
Accordingly, there exists a need for an improved sense amplifier which does not suffer from one or more of the above-noted problems exhibited by conventional sense amplifiers.